Journal: Volume 30, No. 2, 2025
Pages: 53 – 62
DOI: https://doi.org/10.62660/bcstu/2.2025.53
905 Views

Broadband high-linearity voltage buffer with enhanced load-driving capability

Oleksiy Azarov, Serhii Bohomolov, Oleksandr Lukashuk
Received 18.01.2025
Revised 30.04.2025
Accepted 16.06.2025

Abstract

The development of buffer cascades with high linearity, wide bandwidth, and the ability to work with low-impedance or capacitive loads is a pressing issue in modern analogue electronics. The aim of this work was to create a broadband, high-linearity voltage buffer with increased load capacity for use in high-precision systems. The study used computer modelling to analyse the electrical parameters of the proposed cascade and compared it with traditional circuits. A new circuit design approach to building a buffer cascade is proposed, based on an optimised output stage structure and a combination of cascode and push-pull topologies. This configuration reduces output resistance, minimises nonlinear distortion and ensures high signal transmission stability. Modelling results confirmed that the developed buffer has an extended bandwidth, improved frequency characteristics and reduced harmonic distortion over a wide frequency range. In particular, when working with high-capacity loads (up to 200 pF), a significant reduction in signal delay (up to 80-90%) was observed compared to conventional complementary metal-oxide-semiconductor implementations. The assessment of the influence of active element parameters on dynamic stability also confirmed the high reliability of the device under variable load conditions. The research results can be used to improve the performance of analogue-to-digital converters, drivers, amplifiers and control circuits operating in modes with increased current load. The practical value of the development lies in its ability to be integrated into high-precision, energy-efficient and high-speed electronic systems that require stable operation of the buffer cascade under complex load conditions

Keywords

high load; high precision; buffer device; cascode cascade; push-pull structure

References

  1. Allen, P.E., & Holberg, D.R. (2011). CMOS analog circuit design. Oxford: Oxford University Press.
  2. Azarov, O.D., & Stahov, O.Y. (2022). Push-pull voltage buffer devices on bipolar transistors. Herald of Khmelnytskyi National University: Technical Sciences, 1(4), 18-22. doi: 10.31891/2307-5732-2022-311-4-18-22.
  3. Baker, R.J. (2010). CMOS: Circuit design, layout, and simulation. Piscataway: IEEE Press. doi: 10.1002/9780470891179.
  4. Carusone, T.C., Johns, D.A., & Martin, K.W. (2011). Analog integrated circuit design (2nd ed.). Hoboken: John Wiley & Sons, Inc.
  5. Chang, A., & Kong, B. (2020). High-speed rail-to-rail class-ab buffer amplifier with compact, adaptive biasing for FPD applications. Electronics, 9(12), article number 2018. doi: 10.3390/electronics9122018.
  6. Cordell, B. (2010). Designing audio power amplifiers. New York: McGraw-Hill Education.
  7. Fakhfakh, M., Tlelo-Cuautle, E., & Castro-López, R. (2013). Analog/RF and mixed-signal circuit systematic design. Berlin: Springer. doi: 10.1007/978-3-642-36329-0.
  8. Horowitz, P., & Hill, W. (1981). The art of electronics. Physics, 34(3), 67-71. doi: 10.1063/1.2914480.
  9. Kaviani, M., Sharifi, H., Dolatshahi, M., & Navi, K. (2016). Design of low voltage and high-speed bicmos buffer for driving large load capacitor. International Journal of Engineering and Manufacturing, 6(1), 1-9. doi: 10.5815/ ijem.2016.01.01.
  10. Kim, S.K., Son, Y.-S., & Cho, G.H. (2006). Low-power high-slew-rate CMOS buffer amplifier for flat panel display drivers. Electronics Letters, 4(42), 214-215. doi: 10.1049/el:20063898.
  11. Liao, J., Li, P., Gao, Z., Zhi, Y., Fang, Z., & Zhuang, X. (2025). A low noise differential charge amplifier with input buffer stage for toroidal gyroscope. Measurement Science and Technology, 36(5), article number 055112. doi: 10.1088/1361-6501/add314.
  12. Mak, P., & Martins, R.P. (2012). High-/mixed-voltage analog and RF circuit techniques for nanoscale CMOS. New York: Springer. doi: 10.1007/978-1-4419-9539-1.
  13. Mythry, S., & Moni, J. (2019). A bulk-driven, buffer-biased, gain-boosted amplifier for biomedical signal enhancement. Cogent Engineering, 6(1), article number 1658966. doi: 10.1080/23311916.2019.1658966.
  14. Park, H., & Yoo, C. (2013). Effect of buffer cache on storage performance in virtualised environment. Electronics Letters, 4(49), 251-253. doi: 10.1049/el.2012.4069.
  15. Patent No. 158284. (2025). Buffer cascade. Retrieved from https://iprop-ua.com/inv/ec9yoxmd/.
  16. Razavi, B. (2016). Design of analog CMOS integrated circuits (2nd ed.). New York: McGraw-Hill Education.
  17. Roermund, A.H.M., Casier, H., & Steyaert M. (2010). Analog circuit design: Smart data converters, filters on chip, multimode transmitters. Dordrecht: Springer. doi: 10.1007/978-90-481-3083-2.
  18. Rohde, U.L., & Newkirk, D.P. (2000). RF/microwave circuit design for wireless communications. New York: John Wiley & Sons, Inc.
  19. Sansen, W. (2007). Analog design essentials. London: Springer. doi: 10.1007/b135984.
  20. Sharma, D., & Mehra, R. (2011). Low power, delay optimized buffer design using 70nm CMOS technology. International Journal of Computer Applications, 22(3), 13-18. doi: 10.5120/2565-3526.
  21. Tietze, U., & Schenk, C. (2008). Electronic circuits: Handbook for design and applications. Berlin: Springer. doi: 10.1007/978-3-540-78655-9.
  22. Yang, B., Caldwell, T., & Chan Carusone, A. (2025). An energy-efficient pipeline-sar ADC using linearized dynamic amplifiers and input buffer in 22nm FDSOI. IEEE Open Journal of Circuits and Systems, 6, 50-62. doi: 10.1109/ OJCAS.2024.3509746.

Suggested citation

Azarov, О., Bohomolov, S., & Lukashuk, О. (2025). Broadband high-linearity voltage buffer with enhanced load-driving capability. Bulletin of Cherkasy State Technological University, 30(2), 53-62. https://doi.org/10.62660/bcstu/2.2025.53