Tracking-parallel analog-to-digital converter

Oleksiy Azarov; Serhii Bohomolov; Oleksandr Lukashuk

Journal: Volume 31, No. 1, 2026

Pages: 11 – 23

DOI: https://doi.org/10.62660/bcstu/1.2026.1

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Tracking-parallel analog-to-digital converter

Oleksiy Azarov, Serhii Bohomolov, Oleksandr Lukashuk

Received 04.11.2025

Revised 11.02.2026

Accepted 16.03.2026

Published 08.04.2026

Abstract

Amid the rapid evolution of digital signal processing systems, the development of new analog-to-digital converter architectures capable of ensuring high dynamic accuracy without an excessive increase in component count has become a priority. The aim of the work was to improve the dynamic accuracy and speed of the analogto-digital conversion process by developing and investigating an improved tracking-parallel architecture. Methods of automatic control theory, circuit analysis of pulse devices, and mathematical modelling of quantisation errors were applied to achieve the set tasks. The article detailed the operating principle of the proposed device, which is based on the synergy of an inertial tracking loop and a high-speed parallel residue converter. It was proven that introducing a dynamic error measurement stage allows compensating for the output code lag relative to the input signal, typical for traditional tracking systems, thereby eliminating slope overload distortion. The dependence of the input signal dynamic range expansion on the resolution of the parallel block was analytically substantiated, allowing for flexible system adaptation to specific application requirements. Comparative analysis results indicated that the proposed structure provides a significant gain in hardware complexity, enabling high resolution using orders of magnitude fewer precision comparators compared to counterparts. Furthermore, critical requirements for the speed of the operational amplifier and the digital-to-analog converter in the feedback loop were defined to ensure stable operation across the entire frequency range. The practical value of the research lies in developing recommendations for designing competitive integrated circuits oriented towards use in portable devices, medical equipment, and industrial automation systems

Keywords

hybrid architecture; slope overload; dynamic error compensation; residue signal; signal slew rate; hardware efficiency; high-precision

References

Azarov, O.D., Chernyak, O.I., & Stahov, O.Y. (2020). Tracking and bitwise balancing ADC with weight redundancy. Information Technologies and Computer Engineering, 49(3), 37-44. doi: 10.31649/1999-9941-2020-49-3-37-44 .
Baker, R.J. (2008). A high-speed data converter. In CMOS: Mixed-signal circuit design (pp. 301-325). Hoboken: Wiley-IEEE Press. doi: 10.13140/ RG.2.1.5146.6005 .
Carusone, T.C., Johns, D.A., & Martin, K.W. (2011). Analog integrated circuit design (2nd ed.) Hoboken: Wiley.
Fakhfakh, M., Tlelo-Cuautle, E., & Castro-López, R. (2013). Analog/RF and mixed-signal circuit systematic design. Berlin: Springer. doi : 10.1007/978-3-642-36329-0 .
Horowitz, P., & Hill, W. (2015). The art of electronics. New York: Cambridge University Press.
Krishna, K., & Nambath, N. (2024). Review on high-speed dynamic comparators for analog to digital converters. Journal of Circuits, Systems and Computers, 33(13), article number 2430006. doi: 10.1142/S021812662430006X .
Lozada, K.E., Chang, D.J., Oh, D.R., Seo, M.J., & Ryu, S.T. (2024). SAR-assisted energy-efficient hybrid ADCs. IEEE Open Journal of the Solid-State Circuits Society, 4, 163-175. doi: 10.1109/OJSSCS.2024.3472000.
Maloberti, F. (2007). Data converters (pp. 147-170). New York: Springer.
Oh, D.R., Seo, M.J., & Ryu, S.T. (2022). A 7-bit two-step flash ADC with sample-and-hold sharing technique. IEEE Journal of Solid-State Circuits, 57(9), 2791-2801. doi: 10.1109/JSSC.2022.3159569.
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Pelgrom, M.J. (2010). Analog-to-digital conversion. New York: Springer. doi: 10.1007/978-1-4614 1371-4.
Razavi, B. (1995). Principles of data conversion system design. New York: IEEE Press.
Roermund, A.H.M., Casier, H., & Steyaert, M. (2010). Analog circuit design: Smart data converters, filters on chip, multimode transmitters. Dordrecht: Springer. doi: 10.1007/978-90-481-3083-2.
Shahbazi, F., & Shamsi, H. (2025). On the design of a level-crossing ADC with 1-bit DAC and rail-to-rail continuous-time comparator. Analog Integrated Circuits and Signal Processing, 122, article number 31. doi: 10.1007/s10470-025-02344-w .
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Timmermans, M., van Oosterhout, K., Fattori, M., Harpe, P.J.A., Liu, Y.-H., & Cantatore, E. (2024). A 1.8-65 fJ/conv.-step 64 dB SNDR continuous-time level crossing ADC exploiting dynamic self-biasing comparators. IEEE Journal of Solid-State Circuits, 59(4), 1194-1203. doi: 10.1109/JSSC.2024.3352735.
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Xiao, S., Li, F., Hao, T., & Han, G. (2025). Analog-to-digital converter design for diverse performance computingin-memory systems: A comprehensive review. Integrated Circuits and Systems, 2(2), 81-92. doi: 10.23919/ ICS.2025.3571019 .
Zahrai, S.A., & Onabajo, M. (2018). Review of analog-to-digital conversion characteristics and design considerations for the creation of power-efficient hybrid data converters. Journal of Low Power Electronics and Applications, 8(2), article number 12. doi: 10.3390/jlpea8020012.

Suggested citation

Azarov, О., Bohomolov, S., & Lukashuk, О. (2026). Tracking-parallel analog-to-digital converter. Bulletin of Cherkasy State Technological University, 31(1), 11-23. https://doi.org/10.62660/bcstu/1.2026.1

[1] Azarov, O.D., Chernyak, O.I., & Stahov, O.Y. (2020). Tracking and bitwise balancing ADC with weight redundancy. Information Technologies and Computer Engineering, 49(3), 37-44. doi: 10.31649/1999-9941-2020-49-3-37-44 .

[2] Baker, R.J. (2008). A high-speed data converter. In CMOS: Mixed-signal circuit design (pp. 301-325). Hoboken: Wiley-IEEE Press. doi: 10.13140/ RG.2.1.5146.6005 .

[3] Carusone, T.C., Johns, D.A., & Martin, K.W. (2011). Analog integrated circuit design (2nd ed.) Hoboken: Wiley.

[4] Fakhfakh, M., Tlelo-Cuautle, E., & Castro-López, R. (2013). Analog/RF and mixed-signal circuit systematic design. Berlin: Springer. doi : 10.1007/978-3-642-36329-0 .

[5] Horowitz, P., & Hill, W. (2015). The art of electronics. New York: Cambridge University Press.

[6] Krishna, K., & Nambath, N. (2024). Review on high-speed dynamic comparators for analog to digital converters. Journal of Circuits, Systems and Computers, 33(13), article number 2430006. doi: 10.1142/S021812662430006X .

[7] Lozada, K.E., Chang, D.J., Oh, D.R., Seo, M.J., & Ryu, S.T. (2024). SAR-assisted energy-efficient hybrid ADCs. IEEE Open Journal of the Solid-State Circuits Society, 4, 163-175. doi: 10.1109/OJSSCS.2024.3472000.

[8] Maloberti, F. (2007). Data converters (pp. 147-170). New York: Springer.

[9] Oh, D.R., Seo, M.J., & Ryu, S.T. (2022). A 7-bit two-step flash ADC with sample-and-hold sharing technique. IEEE Journal of Solid-State Circuits, 57(9), 2791-2801. doi: 10.1109/JSSC.2022.3159569.

[10] Patent No. 158494. (2025). Tracking-parallel analog-to-digital converter. Retrieved from https://sis.nipo.gov.ua/ uk/search/detail/1841710/.

[11] Pelgrom, M.J. (2010). Analog-to-digital conversion. New York: Springer. doi: 10.1007/978-1-4614 1371-4.

[12] Razavi, B. (1995). Principles of data conversion system design. New York: IEEE Press.

[13] Roermund, A.H.M., Casier, H., & Steyaert, M. (2010). Analog circuit design: Smart data converters, filters on chip, multimode transmitters. Dordrecht: Springer. doi: 10.1007/978-90-481-3083-2.

[14] Shahbazi, F., & Shamsi, H. (2025). On the design of a level-crossing ADC with 1-bit DAC and rail-to-rail continuous-time comparator. Analog Integrated Circuits and Signal Processing, 122, article number 31. doi: 10.1007/s10470-025-02344-w .

[15] Tang, H., Xu, W., Li, H., Wei, B., & Wei, X. (2024). A 0.494.34 μW LC-SAR hybrid ADC with a 10.85-Bit ENOB and 20 KS/s bandwidth. Electronics, 13(6), article number 1078. doi: 10.3390/electronics13061078 .

[16] Tietze, U., Schenk, C., & Gamm, E. (2008). Electronic circuits: Handbook for design and application (2nd ed.). Berlin: Springer. doi: 10.1007/978-3-540-78655-9%20doi.org.

[17] Timmermans, M., van Oosterhout, K., Fattori, M., Harpe, P.J.A., Liu, Y.-H., & Cantatore, E. (2024). A 1.8-65 fJ/conv.-step 64 dB SNDR continuous-time level crossing ADC exploiting dynamic self-biasing comparators. IEEE Journal of Solid-State Circuits, 59(4), 1194-1203. doi: 10.1109/JSSC.2024.3352735.

[18] van de Plassche, R.J. (2003). CMOS integrated analog-to-digital and digital-to-analog converters. Boston: Kluwer Academic Publishers.

[19] Verreault, A., Cicek, P.V., & Robichaud, A. (2024). Oversampling ADC: A review of recent design trends. IEEE Access, 12, 121753-121779. doi: 10.1109/ACCESS.2024.3452589 .

[20] Xiao, S., Li, F., Hao, T., & Han, G. (2025). Analog-to-digital converter design for diverse performance computingin-memory systems: A comprehensive review. Integrated Circuits and Systems, 2(2), 81-92. doi: 10.23919/ ICS.2025.3571019 .

[21] Zahrai, S.A., & Onabajo, M. (2018). Review of analog-to-digital conversion characteristics and design considerations for the creation of power-efficient hybrid data converters. Journal of Low Power Electronics and Applications, 8(2), article number 12. doi: 10.3390/jlpea8020012.